Micron Technology has set an October 21, 2026 technology webinar to lay out what it calls a multigenerational roadmap across DRAM, HBM and NAND, and the timing could not be more pointed. The chipmaker is coming off a quarter in which memory and storage revenue exploded, and the broader AI industry is openly worried that it will not have enough DRAM, HBM or NAND to keep training and serving ever-larger models. Scott DeBoer, Micron’s President and Chief Technology and Products Officer, is scheduled to lead the session, with a question-and-answer period to follow.
The webinar lands at a moment when memory, not compute, has become the bottleneck AI infrastructure planners talk about most. Micron has said next-generation AI infrastructure will require significantly higher bandwidth, capacity and efficiency for moving, storing and accessing data, and the company frames the October 21 session as a chance to explain its technology foundation, customer co-design work, and long-term research aimed at extending its lead “over the next decade and beyond,” according to the announcement posted on GlobeNewswire.
Why AI Infrastructure Is Running Out of Memory
The memory shortage narrative is not abstract anymore. Reports from TrendForce and Blocks and Files describe a market where Micron, Samsung and SK Hynix are prioritizing high-bandwidth memory for AI data centers at the expense of commodity DRAM supply, pushing prices higher across the PC and server markets. Tech Insider has already tracked the knock-on effect on consumer hardware, including DDR5 modules climbing toward $450 for 32GB kits as module makers redirect wafer capacity toward AI memory.
Micron’s own public statements tie that squeeze directly to large language model inference. The company has said AI context lengths are expanding dramatically year over year while memory content per server has roughly doubled over the past three years, a mismatch that explains why HBM bit demand is outrunning conventional server DRAM demand. That dynamic is central to why the October 21 webinar is being watched closely by investors and systems architects alike: the roadmap Micron shows next week will shape how much memory capacity, and at what price, is actually available to AI infrastructure builders through 2028.
Scott DeBoer and What the Webinar Will Cover
Scott DeBoer has held the President and Chief Technology and Products Officer title at Micron, and he is set to lead the October 21 presentation before taking audience questions. According to the webinar notice carried by MarketChameleon, the session is billed as covering innovations across DRAM, HBM and NAND together with Micron’s multigenerational roadmap, rather than a single product announcement.
Micron has not published specific product launch dates, prices, shipment volumes or performance specifications tied to the webinar itself, and nothing in the company’s advance notice names a new part number or architecture reveal. What the announcement does confirm is scope: technology foundation, customer co-design, and long-term research intended to extend Micron’s position “over the next decade and beyond.” Investors will be listening for any signal on how Micron plans to allocate capacity between HBM, server DRAM and NAND as AI demand continues to outpace supply growth.
Inside Micron’s HBM4 Push: From 36GB to 48GB Stacks
The backdrop to the webinar is Micron’s HBM4 ramp, which is already further along than many outside the industry realize. Micron moved its HBM4 36GB 12-high stack into high-volume production earlier in 2026, designed for Nvidia’s Vera Rubin platform. That product exceeds 11 gigabits per second per pin and delivers more than 2.8 terabytes per second of bandwidth per stack, which Micron describes as roughly 2.3 times the bandwidth of HBM3E along with more than 20% better power efficiency, according to Micron’s investor relations materials.
Micron’s roadmap extends beyond that initial part. The company has shown 48GB 16-high HBM4 samples, a higher-capacity configuration that builds on the wider 2048-pin interface, double the bus width used in the prior HBM generation. Micron has said that architecture is built specifically to support demanding AI workloads such as ultra-long-context inference, where a model needs to hold enormous amounts of state in fast memory rather than reloading it from slower storage.
The Custom HBM4E and NV-HBM Partnership With Nvidia
Beyond standard HBM4, Micron has disclosed work with Nvidia on what it calls the industry’s first custom HBM4E implementation, referred to as NV-HBM, intended for future GPU generations and NVLink Fusion platforms. Micron Chief Executive Sanjay Mehrotra has told investors the company sees a strong roadmap ahead for future HBM products and considers the custom HBM4E collaboration with Nvidia a point of pride, a framing that signals memory suppliers are now co-designing silicon alongside GPU vendors rather than selling a commodity part after the fact.
That shift mirrors what Tech Insider has reported on the foundry side, where Samsung tapped TSMC’s 3nm process for its own NVHBM memory chips built for Nvidia. Custom, co-designed HBM is becoming the norm at the high end of the AI accelerator stack, and Micron’s NV-HBM work with Nvidia puts it directly in that race alongside Samsung and SK Hynix.
Breaking Down a $39.8 Billion Memory Quarter
The scale of the AI memory boom shows up clearly in Micron’s recent results. DRAM and HBM revenue reportedly reached $39.8 billion, up 343% year over year, and accounted for 73% of total revenue in the cited quarter, according to reporting from Blocks and Files. NAND revenue, meanwhile, rose 526% to $14.1 billion, representing 26% of total revenue over the same period. Those growth rates are not incremental; they describe a business whose financial center of gravity has shifted almost entirely toward AI-driven memory demand in the span of roughly a year.
| Segment | Revenue | YoY Growth | Share of Total Revenue |
|---|---|---|---|
| DRAM and HBM combined | $39.8 billion | +343% | 73% |
| NAND | $14.1 billion | +526% | 26% |
| DRAM and HBM shipment growth forecast (next 2 years) | Low-to-mid 20% range | Projected | n/a |
| HBM shipment growth vs. conventional DRAM | Faster than DRAM | Projected | n/a |
| CY2027 HBM bit supply contracted | Vast majority already committed | Price increases YoY | n/a |
Micron CEO Sanjay Mehrotra has summed up the shift in blunt terms, telling WhatJobs, “Today there is no AI without memory.” He added that the pricing and demand dynamics that once defined the historically cyclical memory business have changed in kind: “So, the value of memory, that equation has totally changed.” That reframing matters for anyone budgeting AI infrastructure for 2027 and 2028, since it implies memory suppliers now see less reason to discount capacity even as they expand it.
NAND’s New Job: KV-Cache Offload and HDD Replacement
NAND flash is picking up AI-specific duties that go beyond traditional storage. Micron has pointed to key-value cache offload, where inference systems push overflow attention-cache data from expensive HBM and DRAM down to fast SSDs, as an emerging driver of enterprise NAND demand. The company has also flagged NAND as a replacement path for hard-disk-drive infrastructure inside AI data centers, where lower latency and better rack density offset the higher per-gigabyte cost of flash.
That storage squeeze is already visible in finished products. Tech Insider covered how RTX 5090 shortages have pushed GPU prices to multiples of MSRP this year, and the same supply logic, AI buyers absorbing capacity that would otherwise go to consumer and enterprise channels, is now repeating in flash storage as KV-cache offload and AI-optimized SSDs compete with traditional NAND customers for wafer starts.
HBM4 vs. HBM3E: What Actually Changed
The generational leap from HBM3E to HBM4 is the clearest way to understand why Micron, Samsung and SK Hynix are all racing to ship the newer standard. HBM4’s wider interface and higher per-pin speed combine to roughly double the usable bandwidth per stack compared with HBM3E, while also cutting power draw per bit transferred. Micron has said that on its COMPUTEX 2026 measurement methodology, HBM4 36GB 12-high stacks can enable a 2.6-times increase in large language model inference throughput for every twofold increase in memory bandwidth, a ratio that underscores why GPU vendors are willing to pay a premium for the newer memory tier.
| Spec | HBM3E | HBM4 (36GB, 12-high) | HBM4 roadmap (48GB, 16-high) |
|---|---|---|---|
| Pin interface width | 1024-pin | 2048-pin | 2048-pin |
| Per-pin speed | Lower than HBM4 | Greater than 11 Gb/s | Sampling stage |
| Bandwidth per stack | Baseline | Greater than 2.8 TB/s | Higher-capacity target |
| Bandwidth vs. HBM3E | 1x | ~2.3x | Further increase expected |
| Power efficiency vs. HBM3E | Baseline | Over 20% better | Sampling stage |
| Target platform | Current-gen AI accelerators | Nvidia Vera Rubin | Next-gen AI accelerators |
Competitive Landscape: Micron, Samsung and SK Hynix
Micron is not alone in chasing HBM4 volume. Samsung and SK Hynix are both running parallel qualification and ramp programs for Nvidia’s Vera Rubin generation, and reporting from TrendForce has described all three suppliers prioritizing HBM output over commodity DRAM as AI customers lock in multi-year supply agreements. The practical effect for everyone outside the AI data center is less DRAM and NAND available for PCs, phones and consumer SSDs, which is the mechanism behind the DDR5 price increases Tech Insider has tracked separately this year.
Micron’s point of differentiation going into the October 21 webinar is its claim to have already secured agreements covering the vast majority of its calendar-year 2027 HBM bit supply, with year-over-year price increases built in, according to reporting cited by The Register. That kind of forward-contracted certainty is unusual for a historically cyclical commodity business and suggests Micron, like its rivals, is trying to lock in AI-era pricing before the current supply crunch eases.
Historical Context: From Boom-and-Bust to an AI Supercycle
A Cyclical Industry Meets a Structural Shift
Memory has historically been one of the most boom-and-bust corners of the chip industry, with DRAM and NAND prices swinging sharply as supply caught up with, then overshot, demand. Micron’s own CEO has argued that AI has broken that pattern by creating a durable, structural source of demand rather than a cyclical spike. Whether that holds through a full capacity build-out cycle, with new fabs from Micron, Samsung and SK Hynix all coming online over the next several years, is one of the open questions the October 21 webinar is unlikely to fully resolve, but it is the question investors will be asking DeBoer and his team during the Q&A.
Robots Are the Next Memory Customer
One of the more unusual data points to come out of Micron’s recent public commentary concerns humanoid robots rather than data centers. The company has estimated that future high-performance humanoid robots could require more than 200GB of DRAM and several terabytes of NAND storage, with one comparison putting the figure near 4TB of storage, versus roughly 12GB of DRAM and 256GB of storage in today’s service robots. If that forecast holds, physical AI could become a meaningful third leg of memory demand alongside data center AI and traditional computing within the timeframe of Micron’s current roadmap.
Market Impact: Price Pressure Beyond Data Centers
The practical consequence of Micron’s AI memory pivot is visible well outside the data center. PC builders, gamers and enterprise buyers are all competing with AI infrastructure spending for the same wafer capacity, and memory module prices have moved accordingly through 2026. Micron has guided that NAND and DRAM shipments will grow in the low-to-mid 20% range over the next two years, which sounds like healthy supply growth until it is set against HBM shipments growing even faster, meaning commodity memory’s share of total output keeps shrinking relative to AI-earmarked capacity.
That dynamic also connects to the spending side of the AI buildout. Tech Insider has covered how Nvidia’s roughly $500 billion in AI infrastructure commitments and rising B200 GPU prices tied to deals like the Tencent-Oracle agreement are reshaping what AI accelerators cost, and memory is an increasingly large line item inside those system costs as HBM capacity becomes the harder constraint to solve than logic silicon. TSMC, for its part, has reported profit climbing as the AI boom extends, a trend Tech Insider detailed in its coverage of TSMC’s record quarter, underscoring that memory is not the only part of the AI supply chain running hot heading into 2027.
What Micron’s Executives Are Saying
Micron executives have been unusually direct about how AI has reshaped the company’s business model. Sumit Sadana, Micron’s Executive Vice President and Chief Business Officer, said at the company’s COMPUTEX 2026 presentation that “AI context lengths are increasing by 30 times per year, while memory content per server has doubled in the past three years,” a gap he used to explain why memory bandwidth has become the dominant constraint on AI system performance. Sadana went further, stating plainly that “system performance is now driven by memory bandwidth and memory capacity, more than ever before.”
Sadana also framed the HBM4 and Vera Rubin collaboration as part of a broader industry shift toward co-engineered systems rather than off-the-shelf components, saying in Micron’s HBM4 production announcement that “the next era of AI will be defined by tightly integrated platforms developed through joint engineering innovations across the ecosystem.” That comment, tied to Micron’s HBM4 production announcement for Nvidia’s Vera Rubin platform, is consistent with the custom NV-HBM work Micron has disclosed with Nvidia and points toward a future where memory suppliers are named design partners on flagship GPU programs rather than interchangeable vendors.
Predictions: What Comes After HBM4
- Expect Micron to use the October 21 webinar to frame HBM4E and NV-HBM as the bridge to its next full generation, rather than announcing a shipping date for either.
- Pricing on conventional server and consumer DRAM is likely to stay elevated through 2027 as fabs continue prioritizing HBM output, consistent with Micron’s own low-to-mid 20% shipment growth guidance.
- Samsung and SK Hynix will almost certainly respond with their own roadmap disclosures aimed at Nvidia’s Vera Rubin and successor platforms, keeping HBM4E development on a tight, competitive cadence.
- NAND’s role in AI systems will keep expanding past bulk storage, with KV-cache offload and SSD-based memory tiering becoming standard features in next-generation AI server designs.
- If Micron’s humanoid-robot memory estimates hold up, expect robotics original equipment manufacturers to start showing up as named customers in memory earnings calls by 2027 or 2028, alongside hyperscalers and GPU vendors.
What to Watch Before and After October 21
Beyond the webinar itself, the near-term signal to watch is whether Micron, Samsung or SK Hynix announce any new capacity expansion tied specifically to HBM4E or NV-HBM, since that would indicate how quickly the current supply crunch might ease. A second signal is pricing guidance for calendar-year 2027 DRAM and NAND contracts, given Micron has already said the “vast majority” of its 2027 HBM bit supply is contracted with built-in price increases. Coverage from outlets including the Odaily newsflash on the webinar announcement will likely be joined by additional analyst notes once DeBoer’s presentation wraps, and those notes should clarify whether Micron’s roadmap extends meaningfully past HBM4E into a true next-generation standard.
Frequently Asked Questions
When is Micron’s technology webinar?
Micron has scheduled the webinar for Wednesday, October 21, 2026, at 8:00 a.m. Mountain Time, with President and Chief Technology and Products Officer Scott DeBoer leading the presentation and a question-and-answer session to follow.
What will Micron’s roadmap webinar cover?
Micron has said the session will address innovations across DRAM, HBM and NAND, along with its multigenerational roadmap, technology foundation, customer co-design practices, and long-term research goals. No specific new product, price or shipment date has been confirmed ahead of the event.
What is Micron’s HBM4, and how fast is it?
Micron’s HBM4 36GB 12-high stack, already in high-volume production for Nvidia’s Vera Rubin platform, exceeds 11 Gb/s per pin and delivers more than 2.8 TB/s of bandwidth per stack, roughly 2.3 times the bandwidth of HBM3E with more than 20% better power efficiency.
What is NV-HBM, Micron’s custom HBM4E project with Nvidia?
NV-HBM is Micron’s name for what it describes as the industry’s first custom HBM4E implementation, developed jointly with Nvidia for future GPU generations and NVLink Fusion platforms. Specific performance figures and a shipping timeline have not been disclosed.
Why are DRAM and NAND prices rising in 2026?
Memory makers including Micron are directing an increasing share of wafer capacity toward HBM for AI accelerators, which Micron says is growing faster than conventional server DRAM demand. That reallocation has tightened supply for commodity DRAM and NAND, pushing up prices for PCs, servers and consumer storage.
How much did Micron’s memory revenue grow?
Combined DRAM and HBM revenue reportedly reached $39.8 billion, up 331% year over year and representing 73% of total revenue in the cited quarter, while NAND revenue rose 526% to $14.1 billion, or 26% of total revenue, according to reporting from Blocks and Files.
Will humanoid robots need more memory than data centers?
Not more in aggregate, but individually significant. Micron estimates future high-performance humanoid robots could need more than 200GB of DRAM and several terabytes of NAND, compared with roughly 12GB of DRAM and 256GB of storage in today’s service robots, suggesting robotics could become a new, meaningful memory customer segment.
Is Micron’s HBM supply for 2027 already sold out?
Micron has said it has agreements covering the vast majority of its calendar-year 2027 HBM bit supply, with year-over-year price increases built into those agreements, indicating most of next year’s output is already committed to customers.